1. Field of the Invention
The present invention relates to a semiconductor device and particularly, to a complex-type bipolar transistor device comprising a bipolar transistor and a junction-type field effect transistor and its manufacturing method.
2. Background of the Invention
As shown in FIG. 1, a fact that a complex structure high breakdown bipolar transistor is constituted by cascode-connecting a high breakdown voltage junction-type field effect transistor J-FET to a bipolar transistor TR is disclosed, for example, in Japanese laid-open patent publication No. 53-67368.
According to this structure, when a high voltage is applied to a collector side terminal C of the bipolar transistor TR, a depletion layer spreads from a gate junction of the junction-type field effect transistor J-FET giving rise to a pinch-off and as a result, it is interrupted that a high voltage is applied to a collector region of the bipolar transistor TR. That is, as for a collector to emitter voltage Vce of the bipolar transistor TR, only a voltage less than a pinch-off voltage Vp of the junction-type field effect transistor J-FET is applied, thereby making it possible to implement high breakdown voltage in a low withstand voltage bipolar transistor.
In the case of this structure, however, a maximum handling electric current in the bipolar transistor TR is limited to less than a saturation current I dss of the junction-type field effect transistor J-FET. Consequently, when it is tried to increase the saturation current I dss of the junction-type field effect transistor J-FET, there arises a need to make its gate width (channel width) larger, thereby giving rise to an inconvenience that an area occupied by the junction-type field effect transistor J-FET becomes larger.
On the other hand, a complex-type high breakdown voltage bipolar transistor capable of handling at least a large electric current below the saturation current I dss of the junction-type field effect transistor J-FET is proposed by, for example, Japanese laid-open patent publication No. 54-89581.
According to this proposal, for example, as shown in FIG. 2, a collector of an npn type bipolar transistor TR is connected to a source of a junction-type field effect transistor J-FET and at the same time, a base of the bipolar transistor TR is connected to a gate G of the J-FET. In this case, when a high voltage is applied to the collector side terminal C, the junction-type field effect transistor J-FET is put into the pinch-off so that only a voltage less than a pinch-off voltage vp of the J-FET is applied to the bipolar transistor TR, with the result that the high breakdown voltage is implemented in the low operating bipolar transistor TR. In this case, when the bipolar transistor TR is in a state of saturation, the gate of the J-FET is biased in a forward direction, thereby making it possible to handle a large electric current exceeding the saturation electric I dss current of the J-FET.
In these structures, in order to implement the high breakdown voltage of the low operating voltage transistor in the bipolar transistor TR, it is necessary to reduce the pinch-off voltage Vp in the junction-type field effect transistor J-FET.
Also, in the case of these structures, as the part between the source and the drain of junction-type field effect transistor FET is serially connected to the collector of the bipolar transistor TR, there is a demand that the ON resistance of the J-FET is selected as low as possible in order to obtain a high speed responsiveness and a-high frequency characteristic.
However, in order to implement the reduction of the ON resistance in the J-FET and the improvement of the saturation current Idss in the J-FET, it is necessary to increase the impurity concentration in a channel portion. When the concentration in the channel portion is increased, it entails an increase in the pinch-off voltage Vp, thereby making the reduction of the pinch-off voltage Vp incompatible with the reduction of the ON resistance and the improvement of the Idss. Also, in order to increase the Idss and implement the reduction of the ON resistance without increasing the pinch-off voltage Vp, it is conceivable that a gate width is made larger, but in this case, the area occupied by the J-FET increases, thereby impeding high density of a device and implementation of a lesser area.